LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;


ENTITY adder IS
	PORT(currAdd :IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		 nextAdd :OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END adder;
			
ARCHITECTURE behavior OF adder IS
	SIGNAL Cout, Cout1, Cout2, Cout3, Cout4, Cout5, Cout6, Cout7: STD_LOGIC;
	SIGNAL eightBit : STD_LOGIC_VECTOR (7 DOWNTO 0) ;
	
	COMPONENT ula1bit
	PORT(AddSub, Cin, Op :IN  STD_LOGIC ;
	     xi, yi          :IN  STD_LOGIC ;
		 Cout, res    :OUT  STD_LOGIC);
	END COMPONENT;
BEGIN
		eightBit <= "00001000"; 
		stage0: ula1bit PORT MAP ('0', '0',   '1', currAdd(0), eightBit(0), Cout1, nextAdd(0));
		stage1: ula1bit PORT MAP ('0', Cout1, '1', currAdd(1), eightBit(1), Cout2, nextAdd(1));
		stage2: ula1bit PORT MAP ('0', Cout2, '1', currAdd(2), eightBit(2), Cout3, nextAdd(2));
		stage3: ula1bit PORT MAP ('0', Cout3, '1', currAdd(3), eightBit(3), Cout4, nextAdd(3));	
		stage4: ula1bit PORT MAP ('0', Cout4, '1', currAdd(4), eightBit(4), Cout5, nextAdd(4));
		stage5: ula1bit PORT MAP ('0', Cout5, '1', currAdd(5), eightBit(5), Cout6, nextAdd(5));
		stage6: ula1bit PORT MAP ('0', Cout6, '1', currAdd(6), eightBit(6), Cout7, nextAdd(6));
		stage7: ula1bit PORT MAP ('0', Cout7, '1', currAdd(7), eightBit(7), Cout,  nextAdd(7));
END behavior;